.. _biquad:

biquad
======

Description
'''''''''''

|  Biquad IIR filter
| 
|  y(t) = u(t)*b0 + u(t-1)*b1 + u(t-2)*b2 + y(t-1)*(-a1) + y(t-2)*(-a2)
| 
|  Minimizes latency by computing all but u(t)*b0 at end of previous sample.
| 
|  Minimizes resource consumption by using internal
|  DSP registers for between-sample storage.
| 
|  Writing a coefficient holds the filter in reset until address 7 is written.
|  This allows usage of a consistent set of coefficients.
| 

Pinout
''''''

.. _fig:biquad_block:
.. figure:: biquad_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: biquad_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - DATA_WIDTH
     - ?
     - ?
     - 28
     - 
   * - DATA_COUNT
     - ?
     - ?
     - 1
     - 
   * - COEFFICIENT_WIDTH
     - ?
     - ?
     - 25
     - 
   * - DEBUG
     - ?
     - ?
     - 
     - 

Ports
'''''

.. list-table:: biquad_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - sysClk
     - Input
     - 
   * - sysCoefficientStrobe
     - Input
     - 
   * - sysCoefficientAddress[2:0]
     - Input
     - 
   * - sysCoefficientValue[COEFFICIENT_WIDTH-1:0]
     - Input
     - 
   * - dataClk
     - Input
     - 
   * - S_TDATA[(DATA_COUNT*DATA_WIDTH)-1:0]
     - Input
     - 
   * - S_TVALID
     - Input
     - 
   * - S_TREADY
     - Output
     - 
   * - M_TDATA[(DATA_COUNT*DATA_WIDTH)-1:0]
     - Output
     - 
   * - M_TVALID
     - Output
     - 
   * - M_TREADY
     - Input
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`biquad_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:biquad_timing:
.. figure:: biquad_timing.png
    :alt: Timing diagram