.. _complex_mul_flat:

complex_mul_flat
================

Description
'''''''''''

|  TODO:
|  Could potentially save a cycle in the flip-flop, by combining Add and Saturate into 1 cycle

Pinout
''''''

.. _fig:complex_mul_flat_block:
.. figure:: complex_mul_flat_block.png
    :alt: Schematic symbol

Ports
'''''

.. list-table:: complex_mul_flat_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk
     - Input
     - Rising edge clock input; all logic is synchronous in this domain
   * - gate_in
     - Input
     - Flag marking input data valid
   * - x_I[17:0]
     - Input
     - Multiplicand 1, real
   * - x_Q[17:0]
     - Input
     - Multiplicand 1, imag
   * - y_I[17:0]
     - Input
     - Multiplicand 2, real
   * - y_Q[17:0]
     - Input
     - Multiplicand 2, imag
   * - z_I[17:0]
     - Output
     - Result, real
   * - z_Q[17:0]
     - Output
     - Result, imag
   * - z_I_all[35:0]
     - Output
     - Result, real, large
   * - z_Q_all[35:0]
     - Output
     - Result, imag, large
   * - gate_out
     - Output
     - Delayed version of gate_in

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`complex_mul_flat_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:complex_mul_flat_timing:
.. figure:: complex_mul_flat_timing.png
    :alt: Timing diagram