.. _cpxmul_fullspeed:

cpxmul_fullspeed
================

Description
'''''''''''

| 
|  ------------------------------------
|  cpxmul_fullspeed.v
| 
|  Full data-rate pipelined complex multiplier with 3-cycle latency, 4 hw multipliers
|  and 2 adders
|  Expects time-aligned parallel inputs on all data inputs
| 
|  ------------------------------------
| 

Pinout
''''''

.. _fig:cpxmul_fullspeed_block:
.. figure:: cpxmul_fullspeed_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: cpxmul_fullspeed_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - DWI
     - ?
     - ?
     - 18
     - 
   * - OUT_SHIFT
     - ?
     - ?
     - 17
     - Down-shift full-precision result
   * - OWI
     - ?
     - ?
     - 18
     - 

Ports
'''''

.. list-table:: cpxmul_fullspeed_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk
     - Input
     - 
   * - re_a[DWI-1:0]
     - Input
     - 
   * - im_a[DWI-1:0]
     - Input
     - 
   * - re_b[DWI-1:0]
     - Input
     - 
   * - im_b[DWI-1:0]
     - Input
     - 
   * - re_out[OWI-1:0]
     - Output
     - 
   * - im_out[OWI-1:0]
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`cpxmul_fullspeed_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:cpxmul_fullspeed_timing:
.. figure:: cpxmul_fullspeed_timing.png
    :alt: Timing diagram