.. _demand_gpt:

demand_gpt
==========

Description
'''''''''''

| 
|  timing error logic for simple single-input module that
|  requires a fixed gates-per-trig (gpt).

Pinout
''''''

.. _fig:demand_gpt_block:
.. figure:: demand_gpt_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: demand_gpt_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - gpt
     - ?
     - ?
     - 16
     - 

Ports
'''''

.. list-table:: demand_gpt_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk
     - Input
     - 
   * - gate
     - Input
     - 
   * - trig
     - Input
     - 
   * - time_err
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`demand_gpt_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog