.. _double_inte:

double_inte
===========

Description
'''''''''''

|  2 steps of CIC integration. Reset to 0
|  *** N.B: USES AN UNDOCUMENTED IMPLIED DIVIDE-BY-TWO
| 

Pinout
''''''

.. _fig:double_inte_block:
.. figure:: double_inte_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: double_inte_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - dwi
     - ?
     - ?
     - 16
     - data width in
   * - dwo
     - ?
     - ?
     - 28
     - data width out

Ports
'''''

.. list-table:: double_inte_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk
     - Input
     - timespec 8.4 ns
   * - in[dwi-1:0]
     - Input
     - possibly muxed
   * - out[dwo-1:0]
     - Output
     - 
   * - reset
     - Input
     - reset integrator to 0

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`double_inte_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog