.. _evr_ts_cdc:

evr_ts_cdc
==========

Description
'''''''''''

|  Move tinyEVR's 64-bit timestamp to another clock domain
|  Uses Gray codes to get (almost) ideal results.
|  Time delay is one evr_clk plus one-to-two usr_clk cycles.
|  Yes, that's the inevitable clock-domain-crossing jitter.
| 
|  The Gray code scheme fails at the time when ts_tcks gets reset to zero by the evr_pps event.
|  As a workaround, the first _two_ values of the output usr_tcks are forced to zero, every time usr_secs is updated.
| 
|  Obligatory xkcd: https://xkcd.com/2867/

Pinout
''''''

.. _fig:evr_ts_cdc_block:
.. figure:: evr_ts_cdc_block.png
    :alt: Schematic symbol

Ports
'''''

.. list-table:: evr_ts_cdc_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - evr_clk
     - Input
     - 
   * - ts_secs[31:0]
     - Input
     - 
   * - ts_tcks[31:0]
     - Input
     - 
   * - evr_pps
     - Input
     - 
   * - usr_clk
     - Input
     - 
   * - usr_secs[31:0]
     - Output
     - 
   * - usr_tcks[31:0]
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`evr_ts_cdc_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:evr_ts_cdc_timing:
.. figure:: evr_ts_cdc_timing.png
    :alt: Timing diagram