.. _flag_xdomain:

flag_xdomain
============

Pinout
''''''

.. _fig:flag_xdomain_block:
.. figure:: flag_xdomain_block.png
    :alt: Schematic symbol

Ports
'''''

.. list-table:: flag_xdomain_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk1
     - Input
     - 
   * - flagin_clk1
     - Input
     - 
   * - clk2
     - Input
     - 
   * - flagout_clk2
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`flag_xdomain_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog