.. _host_averager:

host_averager
=============

Pinout
''''''

.. _fig:host_averager_block:
.. figure:: host_averager_block.png
    :alt: Schematic symbol

Ports
'''''

.. list-table:: host_averager_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk
     - Input
     - 
   * - data_in[23:0]
     - Input
     - 
   * - data_s
     - Input
     - 
   * - read_s
     - Input
     - 
   * - data_out[31:0]
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`host_averager_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:host_averager_timing:
.. figure:: host_averager_timing.png
    :alt: Timing diagram