.. _iirFilter:

iirFilter
=========

Description
'''''''''''

|  Infinite Impulse Response Filter
| 
|  Chain of biquad elements
| 

Pinout
''''''

.. _fig:iirFilter_block:
.. figure:: iirFilter_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: iirFilter_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - STAGES
     - ?
     - ?
     - 
     - 
   * - DATA_WIDTH
     - ?
     - ?
     - 
     - 
   * - DATA_COUNT
     - ?
     - ?
     - 
     - 
   * - COEFFICIENT_WIDTH
     - ?
     - ?
     - 
     - 
   * - DEBUG
     - ?
     - ?
     - 
     - 
   * - STAGE_ADDRESS_WIDTH
     - ?
     - ?
     - 
     - 

Ports
'''''

.. list-table:: iirFilter_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - sysClk
     - Input
     - 
   * - sysGPIO_Strobe
     - Input
     - 
   * - sysGPIO_Out[31:0]
     - Input
     - 
   * - dataClk
     - Input
     - 
   * - S_TDATA[(DATA_COUNT*DATA_WIDTH)-1:0]
     - Input
     - 
   * - S_TVALID
     - Input
     - 
   * - S_TREADY
     - Output
     - 
   * - M_TDATA[(DATA_COUNT*DATA_WIDTH)-1:0]
     - Output
     - 
   * - M_TVALID
     - Output
     - 
   * - M_TREADY
     - Input
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`iirFilter_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:iirFilter_timing:
.. figure:: iirFilter_timing.png
    :alt: Timing diagram