.. _iq_inter:

iq_inter
========

Description
'''''''''''

| 
|  Second-order CIC interpolation of an IQ data stream
|  Expect input valid for 2 cycles (marked by active-high samp signal)
|  out of 2*N.
|  Well, this is only the integration half of the CIC filter, someone
|  else (e.g., iq_intrp4) needs to do the differentiation.
| 

Pinout
''''''

.. _fig:iq_inter_block:
.. figure:: iq_inter_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: iq_inter_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - dwi
     - ?
     - ?
     - 22
     - data width in
   * - dwo
     - ?
     - ?
     - 18
     - data width out

Ports
'''''

.. list-table:: iq_inter_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk
     - Input
     - timespec 8.4 ns
   * - samp
     - Input
     - 
   * - in[dwi-1:0]
     - Input
     - 
   * - out[dwo-1:0]
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`iq_inter_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog