.. _phase_diff:

phase_diff
==========

Description
'''''''''''

| 
|  DMTD measurement of clock phasing

Pinout
''''''

.. _fig:phase_diff_block:
.. figure:: phase_diff_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: phase_diff_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - order1
     - ?
     - ?
     - 1
     - 
   * - order2
     - ?
     - ?
     - 1
     - 
   * - dw
     - ?
     - ?
     - 14
     - 
   * - delta
     - ?
     - ?
     - 16
     - 

Ports
'''''

.. list-table:: phase_diff_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - uclk1
     - Input
     - unknown clock 1
   * - uclk2
     - Input
     - unknown clock 2
   * - uclk2g
     - Input
     - 
   * - sclk
     - Input
     - sampling clock
   * - rclk
     - Input
     - readout clock (data transfer, local bus)
   * - adv[dw-1:0]
     - Input
     - make adv a runtime variable
   * - err
     - Output
     - 
   * - phdiff_out[dw-2:0]
     - Output
     - 
   * - vfreq_out[dw-1:0]
     - Output
     - 
   * - err_ff
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`phase_diff_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:phase_diff_timing:
.. figure:: phase_diff_timing.png
    :alt: Timing diagram