.. _phasex:

phasex
======

Description
'''''''''''

| 
|  DMTD-inspired investigation into clock phasing
|  No on-chip analysis, but that could be added later once we see the captured patterns

Pinout
''''''

.. _fig:phasex_block:
.. figure:: phasex_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: phasex_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - aw
     - ?
     - ?
     - 10
     - 

Ports
'''''

.. list-table:: phasex_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - uclk1
     - Input
     - unknown clock 1
   * - uclk2
     - Input
     - unknown clock 2
   * - sclk
     - Input
     - sampling clock
   * - rclk
     - Input
     - readout clock (data transfer, local bus)
   * - trig
     - Input
     - 
   * - ready
     - Output
     - 
   * - addr[aw-1:0]
     - Input
     - 
   * - dout[15:0]
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`phasex_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog