.. _timestamp:

timestamp
=========

Description
'''''''''''

|  High-speed cycle counter
| 
|  This module attaches to the slow readout bus used in many
|  LBNL DAQ builds. It provides a 59-bit cycle counter (since chip boot),
|  and an optional timestamp capture register.
| 
|  The 8-bit-wide shift-register-style output is ready to be merged
|  in a "slow" DSP data stream, LSB-first.  Sorry about the byte-order,
|  but it's intrinsic to the mechanism used.
| 
|  Synthesizes to 54 LUTs and 31 Flip flops at 150 MHz in XC3S1000-5 with XST 12.1 (aux_reg=0)
|  Synthesizes to 101 LUTs and 65 Flip flops at 150 MHz in XC3S1000-5 with XST 12.1 (aux_reg=1)
|  59-bit counter will wrap every 182 years if clocked at 100 MHz.

Pinout
''''''

.. _fig:timestamp_block:
.. figure:: timestamp_block.png
    :alt: Schematic symbol

Parameters
''''''''''

.. list-table:: timestamp_param_table
   :header-rows: 1

   * - Name
     - Min
     - Max
     - Default
     - Description
   * - dw
     - ?
     - ?
     - 8
     - 
   * - aux_reg
     - ?
     - ?
     - 0
     - 

Ports
'''''

.. list-table:: timestamp_port_table
   :header-rows: 1

   * - Signal
     - Direction
     - Description
   * - clk
     - Input
     - timespec 6.6 ns
   * - aux_trig
     - Input
     - 
   * - aux_skip
     - Output
     - 
   * - slow_op
     - Input
     - 
   * - slow_snap
     - Input
     - 
   * - shift_in[7:0]
     - Input
     - 
   * - shift_out[7:0]
     - Output
     - 

Implementation and use
''''''''''''''''''''''

The `portable`_ `Verilog`_
implementation can be found in :ref:`timestamp_source`

.. _`portable`: https://en.wikipedia.org/wiki/Software_portability
.. _`Verilog`: https://en.wikipedia.org/wiki/Verilog

Timing Diagram
''''''''''''''

A `GTKWave`_-generated timing diagram is shown below:

.. _`GTKWave`: https://gtkwave.sourceforge.net/

.. _fig:timestamp_timing:
.. figure:: timestamp_timing.png
    :alt: Timing diagram