Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

cim_12x Source File

 1`timescale 1ns / 1ns
 2
 3// Cascaded Integrator Multiplexor
 4module cim_12x #(
 5     parameter dw=32,  // data width of mon_chan output
 6     // should be CIC input data width (18), plus 2 * log2(max sample period)
 7     // also should match width of sr_out port
 8     parameter scale = 18'd65536  // applies to non-downconverted channels
 9     // (inm and outm), opportunity to use values that trigger synthesis
10     // of an actual multiplier to get scaling consistency with
11     // downconverted channels, e.g., 18'd61624 == floor((32/33)^2*2^16)
12) (
13     input clk,
14     input signed [15:0] adca,
15     input signed [15:0] adcb,
16     input signed [15:0] adcc,
17     input signed [15:0] inm,
18     input signed [15:0] outm,
19     input iqs,
20     input signed [15:0] adcx,
21     input signed [17:0] cosa,
22     input signed [17:0] sina,
23     input signed [17:0] cosb,
24     input signed [17:0] sinb,
25     input sample,
26
27     // unprocessed double-integrator output
28     output [dw-1:0] sr_out,
29     output sr_valid,
30     input reset
31);
32
33`ifdef SIMULATE
34`define FILL_BIT 1'bx
35`else
36`define FILL_BIT 1'b0
37`endif
38
39// Each mon_2chan instantiation includes (twice, one for cos, one for sin) the multiplier, double integrator, and sampling/shift-out register
40// Snapshots double-integrator outputs at times flagged by "sample", then shifts the results out on the next twelve cycles.
41wire signed [dw-1:0] s01;  wire g01;
42wire signed [dw-1:0] s03;  wire g03;
43mon_2chan #(.dwi(16), .rwi(dw)) mon01(.clk(clk), .adcf(adca), .mcos(cosa), .msin(sina),
44    .samp(sample), .s_in(s03), .s_out(s01), .g_in(g03), .g_out(g01), .reset(reset));
45
46wire signed [dw-1:0] s05;  wire g05;
47mon_2chan #(.dwi(16), .rwi(dw)) mon03(.clk(clk), .adcf(adcb), .mcos(cosa), .msin(sina),
48    .samp(sample), .s_in(s05), .s_out(s03), .g_in(g05), .g_out(g03), .reset(reset));
49
50wire signed [dw-1:0] s07;  wire g07;
51mon_2chan #(.dwi(16), .rwi(dw)) mon05(.clk(clk), .adcf(adcc), .mcos(cosa), .msin(sina),
52    .samp(sample), .s_in(s07), .s_out(s05), .g_in(g07), .g_out(g05), .reset(reset));
53
54wire signed [dw-1:0] s09;  wire g09;
55mon_2chiq #(.dwi(16), .rwi(dw)) mon07(.clk(clk), .iqd(inm),  .scale(scale), .iqs(iqs),
56    .samp(sample), .s_in(s09), .s_out(s07), .g_in(g09), .g_out(g07), .reset(reset));
57
58wire signed [dw-1:0] s11;  wire g11;
59mon_2chiq #(.dwi(16), .rwi(dw)) mon09(.clk(clk), .iqd(outm), .scale(scale), .iqs(iqs),
60    .samp(sample), .s_in(s11), .s_out(s09), .g_in(g11), .g_out(g09), .reset(reset));
61
62wire signed [dw-1:0] s13;  wire g13;
63mon_2chan #(.dwi(16), .rwi(dw)) mon11(.clk(clk), .adcf(adcx), .mcos(cosb), .msin(sinb),
64    .samp(sample), .s_in(s13), .s_out(s11), .g_in(g13), .g_out(g11), .reset(reset));
65
66// terminate the chain
67assign s13 = {dw{`FILL_BIT}};
68assign g13 = 0;
69
70// use the results of the chain
71assign sr_out = s01;  // data
72assign sr_valid = g01;  // gate
73
74endmodule