Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

Bedrock Modules

DSP

In the DSP directory you can find various various digital signal processing algorithms implemented in platform-independent (portable) Verilog, and their test benches; modules include DDS, Down-conversion, Up-conversion, CIC Filters, Low-Pass filters, High-Pass filters, Mixers.

Contents:

• afterburner
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• async_to_sync_reset_shift
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• banyan
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• banyan_mem
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• biquad
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• ccfilt
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• cic_interp
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• cic_multichannel
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• cic_simple_us
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• cic_wave_recorder
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• cim_12x
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• circle_buf
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• circle_buf_serial
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• complex_freq
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• complex_freq_wrap
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• complex_mul
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• complex_mul_flat
  • Description
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• cordic_mux
  • Description
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• cpxmul_fullspeed
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• data_xdomain
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• demand_gpt
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• double_inte
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• double_inte_smp
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• doublediff
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• doublediff1
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• dpram
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• DSP Digaree Module
  • DSP Digaree
• evr_ts_cdc
  • Description
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• fchan_subset
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• fdownconvert
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• fifo
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• fiq_interp
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• flag_xdomain
  • Pinout
  • Ports
  • Implementation and use
• flevel_set
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• freq_count
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• fwashout
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• half_filt
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• host_averager
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• iirFilter
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• interp1
  • Pinout
  • Ports
  • Implementation and use
• iq_chain4
  • Description
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• iq_deinterleaver
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• iq_deinterleaver_multichannel
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• iq_double_inte
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• iq_inter
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• iq_intrp4
  • Description
  • Pinout
  • Ports
  • Implementation and use
• iq_mixer_multichannel
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• iq_modulator
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• iq_trace
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• isqrt
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• ll_prop
  • Description
  • Pinout
  • Ports
  • Implementation and use
• lpass1
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• minmax
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• mixer
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• mon_2chan
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• mon_2chiq
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• mon_chans
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• multi_counter
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• multi_sampler
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• multiply_accumulate
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• pdetect
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• ph_acc
  • Description
  • Pinout
  • Ports
  • Implementation and use
• phase_diff
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• phaset
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• phasex
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• reg_delay
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• rot_dds
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• rr_arb
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• RTSIM Module
  • RTSIM
• sat_add
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• saturateMath
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• serialize
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• serializer_multichannel
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• shortfifo
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
• ssb_out
  • Description
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• tgen
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• timestamp
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram
• tt800
  • Description
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• upconv
  • Description
  • Pinout
  • Ports
  • Implementation and use
  • Timing Diagram
• xy_pi_clip
  • Description
  • Pinout
  • Parameters
  • Ports
  • Implementation and use
  • Timing Diagram