Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

General Docs

Docs

General documentation

Contents:

• CONTRIBUTING
  • Contributing Guidelines
    • TL;DR
      • Adding a small feature?
      • Adding a large feature?
    • Code of Conduct
    • Contents of a repository
    • Makefiles
    • Reproducible builds
    • Readability
      • A few rules of thumb
      • Verilog
      • Coding and style guidelines
      • Python
    • Testing
• badger README
  • Packet Badger
    • Introduction
    • Block Diagram
    • Self-tests
    • Functionality
    • Example “live” test run
    • Attachment of clients:
    • Other documentation
• doc README
  • Figures
    • Block Diagram
    • Attachment of clients:
    • Memory gateway (localbus) timing:
    • Internal memory addressing:
    • Data path in construct.v:
    • Design study for a precog upgrade
• badger mem_gate
  • Lightweight Address Space Serialization
    • Packet structure
    • Data encoding
    • Practical considerations
    • Implementation and discussion
• badger status
  • Packet Badger Status / Progress
• bmb7_kintex README
• zest README
  • Using zest_setup.py
• build-tools cdc_snitch
  • cdc_snitch Documentation
    • OK1
    • OKX or CDC
    • BAD
    • Memories
    • I/O
    • Verilog input
    • Tool flow
    • Reading the output
    • Dependencies
    • Discussion
• build-tools makefile
  • Makefiles
    • Introduction
    • Example
    • Generalization
    • Configurability
    • Makefile includes
    • Dependencies
    • One more trick
    • Discussion
    • Cross-check
• build-tools newad
  • newad Documentation
    • The workflow of newad
      • Register Attributes
    • Verilog Header Generation
    • Managing clock domains
    • Register names and uniqueness
    • Additional Resources
• dsp README
  • Digital down-conversion
  • IQ interpolation
  • Level set
  • Afterburner [secant interpolation]
  • SSB Out [up-conversion]
• xilinx README
  • Simple generic Xilinx primitives
• guidelines rtl_guidelines
  • RTL Coding Guidelines
    • A - Interfaces
      • A.1 - Interface signal naming
      • A.2 - Keeping interfaces standard
    • B - Signal naming
      • B.1 - Registered and Delayed signals
      • B.2 - Internal or Local signals
      • B.3 - Signal case
      • B.4 - Active-low signals
    • C - Module declaration
      • C.1 - Parameter naming
      • C.2 - Parameter defaults
    • D - Module instantiation
      • D.1 - Instance names
      • D.2 - Unconnected ports
      • D.3 - Port and parameter assignment
    • E - Misc
      • E.1 - TODOs and unfinished code
      • E.2 - Comments
      • E.3 - Precedence rules
• localbus README
  • Localbus support
• localbus jit_rad
  • jit_rad: Just In Time Readback Across Domains
    • Code
    • Prerequisites and usage
  • To do:
• i2cbridge README
  • Yet another I2C (really TWI) bridge/controller/interface
    • Primary goals
    • Usage
    • Design
    • Workstation requirements
    • Programming
  • Other notes
  • To do
• idelay_scanner README
  • idelay_scanner
• common README
  • LEEP
  • Other files
    • get_raw_adcs.py
• comms_top README
  • COMMS TOP
    • Architecture
  • Ethernet and Local Bus
  • ChitChat
    • MGT Setup
  • TCL-based MGT configuration
    • (Self-)Testing
• bmb7_cu README
  • TODO
• marble_family README
  • Context
  • Firmware related info
  • Build FW and program Marble
  • Zest related initialization
    • Clock frequency
    • PYTHONPATH setup
    • Configure zest and run oscope
• test_marble_family README
  • Marble1
    • Extras
• i2c README
  • Marble Platform Support for I2CBridge Programming
    • Usage:
    • Demos:
      • Generate program and memory maps
      • Test 1: Decode the program
      • Test 2: Decode the program without platform awareness
      • Test 3: Test assembler violations
• rtsim README
  • full-speed full-featured cavity simulation, to exercise LLRF controls
    • Larry Doolittle, LBNL, May-June 2014
      • Get started
• chitchat README
  • ChitChat Serial Protocol
    • Packet format
    • Link Up detection
    • Error detection
    • Throughput and latency
• chitchat chitchat_txrx_wrap
  • Clocking
  • Transceiver connection
  • Data flow
  • Status/Debug signals
• picorv32 README
  • RISC-V SOC
  • Tested hardware platforms
  • Projects at LBNL
  • Tools needed
    • Cross compiling tools
    • Synthesis tool
  • Features
    • System simulation
    • Peripheral support
    • Xilinx AXI-lite bus bridge
    • LBNL localbus bridge
    • System synthesize
    • FPGA config
    • Reload CPU program without re-synthesizing
    • Memory size
  • Getting started
• badger_lwip README
  • badger_lwip
  • Instructions
    • Setup the tap interface
    • Run it
    • (Bridging)[https://wiki.archlinux.org/title/Network_bridge] tap0
• fv README
  • Formal verification
• lb_bridge README
  • localbus shared memory testbench