Attention

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cordic_mux Source File

 1`timescale 1ns / 1ns
 2
 3// in this module,
 4// data flows from in_iq, through the CORDIC, to out_mp
 5// data flows from in_xy and in_ph, through the CORDIC, to out_iq
 6// delay is 23 clock cycles
 7
 8//               1   2   3   4         23  24  25  26  27
 9// clk      -\_/-\_/-\_/-\_/-\_/-..._/-\_/-\_/-\_/-\_/-\_/-\
10// phase    ___/---\___/---\___/-..._/---\___/---\___/---\__
11// in_iq     .   I   Q   .   .         .   .   .   .   .
12// out_mp    .   .   .   .   .         .   M   P   .   .
13// in_xy     .   .   X   Y   .         .   .   .   .   .
14// in_ph     .   .   .   P   .         .   .   .   .   .
15// out_iq    .   .   .   .   .         .   .   I   Q   .
16module cordic_mux(
17     input clk,
18     input phase,
19     // rectangular ports
20     input  signed [17:0] in_iq,
21     output signed [17:0] out_iq,
22     // polar ports
23     input  signed [17:0] in_xy,
24     input  signed [18:0] in_ph,
25     output signed [17:0] out_mp
26);
27
28wire signed [17:0] in_iq_se = {in_iq[17],in_iq[17:1]};
29reg  signed [17:0] in_iq_hold=0;
30reg  signed [17:0] in_xy_hold=0;
31always @(posedge clk) begin
32     in_iq_hold <= in_iq_se;
33     in_xy_hold <= in_xy;
34end
35
36// CORDIC input selection
37wire signed [17:0] feed_x = phase ? in_xy_hold : in_iq_hold;
38wire signed [17:0] feed_y = phase ? in_xy      : in_iq_se;
39wire signed [18:0] feed_z = phase ? in_ph      : 0;
40
41// CORDIC instantiation
42wire signed [17:0] out_x, out_y;
43wire signed [18:0] out_z;
44cordicg_b22 #(.nstg(20), .width(18)) cordic(.clk(clk), .opin({1'b0,~phase}),
45     .xin(feed_x), .yin(feed_y), .phasein(feed_z),
46     .xout(out_x), .yout(out_y), .phaseout(out_z)
47);
48
49// output stream generation
50reg signed [17:0] hold_y=0, out_iq_r=0, out_mp_r=0;
51reg signed [18:0] hold_z=0;
52always @(posedge clk) begin
53     hold_y <= out_y;
54     hold_z <= out_z;
55     out_iq_r <= phase ? hold_y : out_x;
56     out_mp_r <= phase ? out_x : hold_z[18:1];
57end
58
59assign out_iq = out_iq_r;
60assign out_mp = out_mp_r;
61
62endmodule