Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
cpxmul_fullspeed Source File
1`timescale 1ns / 1ns
2
3// ------------------------------------
4// cpxmul_fullspeed.v
5//
6// Full data-rate pipelined complex multiplier with 3-cycle latency, 4 hw multipliers
7// and 2 adders
8// Expects time-aligned parallel inputs on all data inputs
9//
10// ------------------------------------
11
12module cpxmul_fullspeed #(
13 parameter DWI = 18,
14 parameter OUT_SHIFT = 17, // Down-shift full-precision result
15 parameter OWI = 18
16) (
17 input clk,
18 input signed [DWI-1:0] re_a,
19 input signed [DWI-1:0] im_a,
20 input signed [DWI-1:0] re_b,
21 input signed [DWI-1:0] im_b,
22 output signed [OWI-1:0] re_out,
23 output signed [OWI-1:0] im_out
24);
25
26 // (re_a + j*im_a) * (re_b + j*im_b) =
27 // (re_a*re_b - im_a*im_b) + j(re_a*im_b + im_a*re_b)
28 reg signed [DWI*2-1:0] mul1=0, mul2=0, mul3=0, mul4=0;
29 reg signed [DWI*2-1:0] sum1=0, sum2=0, sum3=0;
30 reg signed [DWI*2-OUT_SHIFT-1:0] sum1_r=0, sum2_r=0;
31
32`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
33 always @(posedge clk) begin
34 mul1 <= re_a*re_b;
35 mul2 <= im_a*im_b;
36 mul3 <= re_a*im_b;
37 mul4 <= im_a*re_b;
38 sum1 <= mul1 - mul2;
39 sum2 <= mul3 + mul4;
40 sum1_r <= sum1[DWI*2-1:OUT_SHIFT];
41 sum2_r <= sum2[DWI*2-1:OUT_SHIFT];
42 end
43
44 assign re_out = `SAT(sum1_r, DWI*2-OUT_SHIFT-1, OWI-1);
45 assign im_out = `SAT(sum2_r, DWI*2-OUT_SHIFT-1, OWI-1);
46`undef SAT
47
48endmodule