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iq_chain4 Source File

 1`timescale 1ns / 1ns
 2
 3// Filters and decimates four I-Q multiplexed data streams
 4// down to a single data path
 5// Uses second-order CIC filtering.
 6// Larry Doolittle, LBNL, 2014
 7
 8module iq_chain4(
 9     input clk,
10     input sync,
11     input signed [17:0] in1,
12     input signed [17:0] in2,
13     input signed [17:0] in3,
14     input signed [17:0] in4,
15     output signed [21:0] out
16);
17
18reg sync1=0;
19always @(posedge clk) sync1 <= sync;
20wire samp = sync | sync1;
21
22wire signed [21:0] o1, o2, o3, o4;
23iq_double_inte #(.dwi(18), .dwo(22)) di1(.clk(clk), .in(in1), .out(o1));
24iq_double_inte #(.dwi(18), .dwo(22)) di2(.clk(clk), .in(in2), .out(o2));
25iq_double_inte #(.dwi(18), .dwo(22)) di3(.clk(clk), .in(in3), .out(o3));
26iq_double_inte #(.dwi(18), .dwo(22)) di4(.clk(clk), .in(in4), .out(o4));
27
28wire signed [21:0] s1, s2, s3, s4;
29reg signed [21:0] c1=0, c2=0, c3=0, c4=0;
30always @(posedge clk) begin
31     c1 <= s2;
32     c2 <= s3;
33     c3 <= s4;
34end
35
36serialize #(.dwi(22)) ser1(.clk(clk), .samp(samp), .data_in(o1), .stream_in(c1), .stream_out(s1), .gate_in(1'b1));
37serialize #(.dwi(22)) ser2(.clk(clk), .samp(samp), .data_in(o2), .stream_in(c2), .stream_out(s2), .gate_in(1'b1));
38serialize #(.dwi(22)) ser3(.clk(clk), .samp(samp), .data_in(o3), .stream_in(c3), .stream_out(s3), .gate_in(1'b1));
39serialize #(.dwi(22)) ser4(.clk(clk), .samp(samp), .data_in(o4), .stream_in(c4), .stream_out(s4), .gate_in(1'b1));
40
41wire signed [21:0] d_out;
42doublediff #(.dw(22), .dsr_len(8)) dd(.clk(clk), .d_in(s1), .g_in(1'b1), .d_out(d_out));
43assign out = d_out;
44
45endmodule