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multi_sampler Source File

 1`timescale 1ns / 1ns
 2
 3/** MULTI SAMPLER
 4    Multi-purpose sampling signal generation with the following features:
 5    - Arbitrary base sampling period, defined as a fraction of input clock
 6      qualified with external trigger (ext_trig)
 7    - Main sampling signal
 8    - Three configurable downsampling strobes, defined w.r.t base sampling period
 9    - Downsampling strobe generation can be disabled to save HW if not required
10**/
11
12module multi_sampler #(
13   parameter sample_period_wi=8,
14   parameter dsample0_en=0,
15   parameter dsample0_wi=8,
16   parameter dsample1_en=0,
17   parameter dsample1_wi=8,
18   parameter dsample2_en=0,
19   parameter dsample2_wi=8
20) (
21   input                        clk,
22   input                        reset,
23   input                        ext_trig,
24   input [sample_period_wi-1:0] sample_period,
25   input [dsample0_wi-1:0]      dsample0_period,
26   input [dsample1_wi-1:0]      dsample1_period,
27   input [dsample2_wi-1:0]      dsample2_period,
28   output                       sample_out,
29   output                       dsample0_stb,
30   output                       dsample1_stb,
31   output                       dsample2_stb
32);
33
34`ifdef SIMULATE
35   localparam INITVAL=1;
36`else
37   localparam INITVAL=0; // Longer startup
38`endif
39
40   reg [sample_period_wi-1:0] samp_per_r = 0;
41   reg [sample_period_wi-1:0] base_count = 0;
42   reg [dsample0_wi-1:0]      ds0_count = INITVAL;
43   reg [dsample1_wi-1:0]      ds1_count = INITVAL;
44   reg [dsample2_wi-1:0]      ds2_count = INITVAL;
45   reg sample_out_l = 0;
46
47   // Base-timing generation
48   always @(posedge clk) begin
49      sample_out_l <= 0;
50      if (reset) begin
51        samp_per_r <= 0;
52        base_count <= 0;
53      end else if (ext_trig) begin
54         samp_per_r <= sample_period;
55
56         base_count <= (base_count == (sample_period-1)) ? 0 : base_count+1;
57
58         // Restart count on sample_period change
59         if ((sample_period != samp_per_r) && |base_count) base_count <= 0;
60
61         sample_out_l <= (base_count == 0);
62      end
63   end
64   assign sample_out = sample_out_l;
65
66   generate if (dsample0_en) begin : g_dsample0
67      always @(posedge clk) begin
68         if (sample_out_l)
69            ds0_count <= (ds0_count == 1) ? dsample0_period : ds0_count-1;
70      end
71      assign dsample0_stb = ds0_count==1;
72   end else begin : ng_dsample0
73      assign dsample0_stb = 0;
74   end endgenerate
75
76   generate if (dsample1_en) begin : g_dsample1
77      always @(posedge clk) begin
78         if (sample_out_l)
79            ds1_count <= (ds1_count == 1) ? dsample1_period : ds1_count-1;
80      end
81      assign dsample1_stb = ds1_count==1;
82   end else begin : ng_dsample1
83      assign dsample1_stb = 0;
84   end endgenerate
85
86   generate if (dsample2_en) begin : g_dsample2
87      always @(posedge clk) begin
88         if (sample_out_l)
89            ds2_count <= (ds2_count == 1) ? dsample2_period : ds2_count-1;
90      end
91      assign dsample2_stb = ds2_count==1;
92   end else begin : ng_dsample2
93      assign dsample2_stb = 0;
94   end endgenerate
95
96endmodule