Attention

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ph_acc Source File

 1`timescale 1ns / 1ns
 2
 3// Phase accumulator, to act as basis for DDS (direct digital synthesizer).
 4// Tuned to allow 32-bit control, divided 20-bit high and 12-bit low,
 5// which gets merged to 32-bit binary when modulo is zero.
 6// But also supports non-binary frequencies: see the modulo input port.
 7module ph_acc(
 8     input clk,  // Rising edge clock input; all logic is synchronous in this domain
 9     input reset,  // Active high, synchronous with clk
10     input en,   // Enable
11     output [18:0] phase_acc,  // Output phase word
12     input [19:0] phase_step_h,  // High order (coarse, binary) phase step
13     input [11:0] phase_step_l,  // Low order (fine, possibly non-binary) phase step
14     input [11:0] modulo  // Encoding of non-binary modulus; 0 means binary
15);
16
17reg carry=0, reset1=0;
18reg [19:0] phase_h=0, phase_step_hp=0;
19reg [11:0] phase_l=0;
20always @(posedge clk) if (en) begin
21     {carry, phase_l} <= reset ? 13'b0 : ((carry ? modulo : 12'b0) + phase_l + phase_step_l);
22     phase_step_hp <= phase_step_h;
23     reset1 <= reset;
24     phase_h <= reset1 ? 20'b0 : (phase_h + phase_step_hp + carry);
25end
26assign phase_acc=phase_h[19:1];
27
28endmodule