Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

ph_acc Source File

 1`timescale 1ns / 1ns
 2
 3// Phase accumulator, to act as basis for DDS (direct digital synthesizer).
 4// Tuned to allow 32-bit control, divided 20-bit high and 12-bit low,
 5// which gets merged to 32-bit binary when modulo is zero.
 6// But also supports non-binary frequencies: see the modulo input port.
 7
 8// Note that phase_step_h and phase_step_l combined fit in a 32-bit word.
 9// This is intentional, to allow atomic updates of the two controls
10// in 32-bit systems.  Indeed, when modulo==0, those 32 bits can be considered
11// a single phase step increment
12
13// The phase generation algorithm
14// 0. The phase increments for dds are generated using a technique described
15// in these 2 places:
16// Section: PROGRAMMABLE MODULUS MODE in:
17//  https://www.analog.com/media/en/technical-documentation/data-sheets/ad9915.pdf
18//  (AND) https://en.wikipedia.org/wiki/Bresenham%27s_line_algorithm
19//  Basically, increment the phase step at a coarse resolution, accumulate the
20//  error on the side, and when that error accumulates to the lowest bit of
21//  the coarse counter, add an extra 1 to the following phase step.
22// 1. phase_step_h is the coarse (20 bit) integer truncated phase increment for
23//  the cordic. There is a 1-bit increment of phase that comes from
24//  accumulating residue phase.
25// 2. This residue phase is accumulating in steps of phase_step_l, in a 12-bit
26//  counter.
27// 3. However, there will be an extra residue even for this 12-bit counter,
28// which is the modulus, and this added as an offset when the counter crosses 0
29
30// 12-bit modulo supports largest known periodicity in a suggested LLRF system,
31// 1427 for JLab.  For more normal periodicities, use a multiple to get finer
32// granularity.
33// Note that the downloaded modulo control is the 2's complement of the
34// mathematical modulus.
35// e.g., SSRF IF/F_s ratio 8/11, use
36//     modulo = 4096 - 372*11 = 4
37//     phase_step_h = 2^20*8/11 = 762600
38//     phase_step_l = (2^20*8%11)*372 = 2976
39// e.g., Argonne RIA test IF/F_s ratio 9/13, use
40//     modulo = 4096 - 315*13 = 1
41//     phase_step_h = 2^20*9/13 = 725937
42//     phase_step_l = (2^20*9%13)*315 = 945
43
44module ph_acc(
45     input clk,  // Rising edge clock input; all logic is synchronous in this domain
46     input reset,  // Active high, synchronous with clk
47     input en,   // Enable
48     output [18:0] phase_acc,  // Output phase word
49     input [19:0] phase_step_h,  // High order (coarse, binary) phase step
50     input [11:0] phase_step_l,  // Low order (fine, possibly non-binary) phase step
51     input [11:0] modulo  // Encoding of non-binary modulus; 0 means binary
52);
53
54reg carry=0, reset1=0;
55reg [19:0] phase_h=0, phase_step_hp=0;
56reg [11:0] phase_l=0;
57always @(posedge clk) if (en) begin
58     {carry, phase_l} <= reset ? 13'b0 : ((carry ? modulo : 12'b0) + phase_l + phase_step_l);
59     phase_step_hp <= phase_step_h;
60     reset1 <= reset;
61     phase_h <= reset1 ? 20'b0 : (phase_h + phase_step_hp + carry);
62end
63assign phase_acc=phase_h[19:1];
64
65endmodule