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reg_delay Source File

 1`timescale 1ns / 1ns
 2
 3// Encapsulation of a register delay, z^{-n} in DSP-speak
 4// Properly handles odd-ball special cases like len==0
 5module reg_delay #(
 6     parameter dw=16,  // Width of data
 7     parameter len=4   // Cycles to delay
 8) (
 9     input clk,  // Rising edge clock input; all logic is synchronous in this domain
10     input reset,  // Please tie to 0 if you can; see below
11     input gate,  // Enable processing
12     input [dw-1:0] din,  // Input data
13     output [dw-1:0] dout  // Output data
14);
15
16// When used in a Xilinx chip, ideally this logic is turned into
17// a bunch of SRL16 shift registers or similar.  That works only if
18// our reset port is tied to 1'b0 at instantiation site.
19generate if (len > 1) begin: usual
20     reg [dw*len-1:0] shifter=0;
21     always @(posedge clk) begin
22             if (gate) shifter <= {shifter[dw*len-1-dw:0],din};
23             if (reset) shifter <= 0;
24     end
25     assign dout = shifter[dw*len-1:dw*len-dw];
26end else if (len > 0) begin: degen1
27     reg [dw*len-1:0] shifter=0;
28     always @(posedge clk) begin
29             if (gate) shifter <= din;
30             if (reset) shifter <= 0;
31     end
32     assign dout = shifter[dw*len-1:dw*len-dw];
33end else if (len == 0) begin: degen0
34     assign dout = din;
35end else begin: bad
36     assign dout = din[-1:0];
37end
38endgenerate
39
40endmodule