Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

rot_dds Source File

 1// Phase Rotating Direct Digital Synthesis of sin/cos
 2// 18 bit output coming from cordicg
 3// Note that phase_step_h and phase_step_l combined fit in a 32-bit word.
 4// This is intentional, to allow atomic updates of the two controls
 5// in 32-bit systems.  Indeed, when modulo==0, those 32 bits can be considered
 6//
 7// a simple fast binary DDS control for quirky (non-binary-rounding) phase
 8// steps like:
 9// 7/33 for LCLS-II
10// 8/11 for SSRF
11// 9/13 for Argonne RIA
12//
13// Synthesizes to ??? slices at ??? MHz in XC3Sxxx-4 using XST-??
14//
15
16`timescale 1ns / 1ns
17
18module rot_dds(
19     input clk,  // timespec 9.0 ns
20     input reset,  // active high, synchronous with clk
21     output signed [17:0] sina,
22     output signed [17:0] cosa,
23     input [19:0] phase_step_h,
24     input [11:0] phase_step_l,
25     input [11:0] modulo
26);
27
28// 2^17/1.64676 = 79594, use a smaller value to keep CORDIC round-off
29// from overflowing the output
30parameter lo_amp = 18'd79590;
31// Sometimes we cheat and use slightly smaller values than above,
32// to make other computations fit better.
33
34wire [18:0] phase_acc;
35ph_acc ph_acc_i (
36  .clk(clk), .reset(reset), .en(1'b1), // input
37  .phase_acc(phase_acc), // output [18:0]
38  .phase_step_h(phase_step_h), // input [19:0]
39  .phase_step_l(phase_step_l), // input [11:0]
40  .modulo(modulo) // input [11:0]
41);
42// See rot_dds_config
43
44cordicg_b22 #(.nstg(20), .width(18), .def_op(0)) trig(.clk(clk), .opin(2'b00),
45     .xin(lo_amp), .yin(18'd0), .phasein(phase_acc),
46// 2^17/1.64676 = 79594, use a smaller value to keep CORDIC round-off
47// from overflowing the output
48     .xout(cosa), .yout(sina));
49
50endmodule