Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
tt800 Source File
1`timescale 1ns / 1ns
2
3// A synthesizable Verilog program for TT800
4// Adapted from Twisted GFSR Generators II
5// Makoto Matsumoto and Yoshiharu Kurita
6// December 2, 1992
7// http://www.math.sci.hiroshima-u.ac.jp/~m-mat/eindex.html
8
9module tt800(
10 input clk, // timespec 3.0 ns
11 input en,
12 input init,
13 input [31:0] initv,
14 output [31:0] y
15);
16
17wire [31:0] tap1, tap2;
18wire [31:0] x = tap1 ^ (tap2>>1) ^ ({32{tap2[0]}}&32'h8ebfd028);
19wire [31:0] newv = init ? initv : x;
20reg_delay #(.dw(32), .len(18)) d1(.clk(clk), .reset(1'b0), .gate(en), .din(newv), .dout(tap1));
21reg_delay #(.dw(32), .len(7)) d2(.clk(clk), .reset(1'b0), .gate(en), .din(tap1), .dout(tap2));
22
23wire [31:0] y1 = tap2 ^ ((tap2 << 7) & 32'h2b5b2500); /* s and b */
24wire [31:0] y2 = y1 ^ ((y1 << 15) & 32'hdb8b0000); /* t and c */
25wire [31:0] y3 = y2 ^ (y2 >> 16); /* update from 1996 by Makoto Matsumoto */
26reg [31:0] y_r=0;
27always @(posedge clk) if (en) y_r <= y3; // use tap2 for T800
28assign y = y_r;
29endmodule