Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

doc README

Figures

This directory holds diagrams that document various aspects of Packet Badger. The Verilog source code refers to these as appropriate. Some of them are also used by the README.md in the root directory.

All the .eps files here are created and editable by xcircuit. Rules in the associated Makefile convert them to the web-compatible SVG format.

Block Diagram

block diagram

Attachment of clients:

client interface timing diagram

Memory gateway (localbus) timing:

mem_gateway timing

Internal memory addressing:

memory access diagram

Data path in construct.v:

data path diagram

Design study for a precog upgrade

timing diagram