Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

async_to_sync_reset_shift

Pinout

Schematic symbol

Parameters

Table 3 async_to_sync_reset_shift_param_table
Name	Min	Max	Default	Description
LENGTH	?	?	8
INPUT_POLARITY	?	?	1
OUTPUT_POLARITY	?	?	1

Ports

Table 4 async_to_sync_reset_shift_port_table
Signal	Direction	Description
clk	Input
Pinput	Input
Poutput	Output

Implementation and use

The portable Verilog implementation can be found in async_to_sync_reset_shift Source File