Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

doublediff

Description

Differentiate when the gate is HIGH

Pinout

Parameters

Table 45 doublediff_param_table

Name	Min	Max	Default	Description
dw	?	?	28
dsr_len	?	?	4

Ports

Table 46 doublediff_port_table

Signal	Direction	Description
clk	Input
d_in[dw-1:0]	Input	Input data
g_in	Input	A gate when set to high differentiates input data
d_out[dw-1:0]	Output
g_out	Output

Implementation and use

The portable Verilog implementation can be found in doublediff Source File