Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

double_inte_smp

Description

Pinout

Schematic symbol

Parameters

Table 43 double_inte_smp_param_table
Name	Min	Max	Default	Description
dwi	?	?	16	data width in
dwo	?	?	28	data width out. When used for decimation, output width should

Ports

Table 44 double_inte_smp_port_table
Signal	Direction	Description
strobe	Input
clk	Input
reset	Input
stb_in	Input
in[dwi-1:0]	Input
out[dwo-1:0]	Output

Implementation and use

The portable Verilog implementation can be found in double_inte_smp Source File