Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

demand_gpt

Description

timing error logic for simple single-input module that

requires a fixed gates-per-trig (gpt).

Pinout

Parameters

Table 39 demand_gpt_param_table

Name	Min	Max	Default	Description
gpt	?	?	16

Ports

Table 40 demand_gpt_port_table

Signal	Direction	Description
clk	Input
gate	Input
trig	Input
time_err	Output

Implementation and use

The portable Verilog implementation can be found in demand_gpt Source File