Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

double_inte

Description

2 steps of CIC integration. Reset to 0

*** N.B: USES AN UNDOCUMENTED IMPLIED DIVIDE-BY-TWO

Pinout

Parameters

Table 41 double_inte_param_table

Name	Min	Max	Default	Description
dwi	?	?	16	data width in
dwo	?	?	28	data width out

Ports

Table 42 double_inte_port_table

Signal	Direction	Description
clk	Input	timespec 8.4 ns
in[dwi-1:0]	Input	possibly muxed
out[dwo-1:0]	Output
reset	Input	reset integrator to 0

Implementation and use

The portable Verilog implementation can be found in double_inte Source File