Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

iq_double_inte

Description

Double-integrator for interleaved I-Q samples

Front end of a second-order CIC, see iq_chain4

Pinout

Parameters

Table 78 iq_double_inte_param_table

Name	Min	Max	Default	Description
dwi	?	?	16	data width in
dwo	?	?	28	data width out

Ports

Table 79 iq_double_inte_port_table

Signal	Direction	Description
clk	Input	timespec 8.4 ns
in[dwi-1:0]	Input	IQ muxed
out[dwo-1:0]	Output

Implementation and use

The portable Verilog implementation can be found in iq_double_inte Source File