Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
minmax
Description
Simple always-on minmax finder, designed to be applied to ADC inputs.
reset is single-cycle, designed such that you can capture the outputs
on the same cycle as you apply the reset, resulting in no blind cycles.
Pinout
Parameters
Name |
Min |
Max |
Default |
Description |
|---|---|---|---|---|
width |
? |
? |
14 |
Ports
Signal |
Direction |
Description |
|---|---|---|
clk |
Input |
|
xin[width-1:0] |
Input |
|
reset |
Input |
|
xmin[width-1:0] |
Output |
|
xmax[width-1:0] |
Output |
Implementation and use
The portable Verilog implementation can be found in minmax Source File