Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

mixer

Description

Pinout

Parameters

Table 96 mixer_param_table

Name	Min	Max	Default	Description
NORMALIZE	?	?	0
NUM_DROP_BITS	?	?	1	Number of bits to drop at the output.
dwi	?	?	16	Width of ADC input
davr	?	?	4	Guard bits to keep at output. E.g. if downstream
dwlo	?	?	18	Width of local-oscillator input

Ports

Table 97 mixer_port_table

Signal	Direction	Description
clk	Input
adcf[dwi-1:0]	Input
mult[dwlo-1:0]	Input
mixout[dwi+davr-1:0]	Output

Implementation and use

The portable Verilog implementation can be found in mixer Source File