Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

cim_12x

Description

Cascaded Integrator Multiplexor

Pinout

Parameters

Table 21 cim_12x_param_table

Name	Min	Max	Default	Description
dw	?	?	32	data width of mon_chan output
scale	?	?	18

Ports

Table 22 cim_12x_port_table

Signal	Direction	Description
clk	Input
adca[15:0]	Input
adcb[15:0]	Input
adcc[15:0]	Input
inm[15:0]	Input
outm[15:0]	Input
iqs	Input
adcx[15:0]	Input
cosa[17:0]	Input
sina[17:0]	Input
cosb[17:0]	Input
sinb[17:0]	Input
sample	Input
sr_out[dw-1:0]	Output
sr_valid	Output
reset	Input

Implementation and use

The portable Verilog implementation can be found in cim_12x Source File