Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

ll_prop

Description

Keep the interface to this module simple:

all IQ inputs and outputs are co-phased,

i.e., I values when iq is high, Q values when iq is low.

Pinout

Ports

Table 91 ll_prop_port_table

Signal	Direction	Description
clk	Input
iq	Input
in_iq[17:0]	Input
out_iq[17:0]	Output
coarse_scale[1:0]	Input	max gain 8, 64, 512, 4096
set_iq[17:0]	Input
gain_iq[17:0]	Input
drive_iq[17:0]	Input

Implementation and use

The portable Verilog implementation can be found in ll_prop Source File