Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

flag_xdomain

Pinout

Ports

Table 60 flag_xdomain_port_table

Signal	Direction	Description
clk1	Input
flagin_clk1	Input
clk2	Input
flagout_clk2	Output

Implementation and use

The portable Verilog implementation can be found in flag_xdomain Source File