Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

data_xdomain

Description

clk_out must be more than twice as fast as the gate_in rate.

Pinout

Schematic symbol

Parameters

Table 37 data_xdomain_param_table
Name	Min	Max	Default	Description
size	?	?	16

Ports

Table 38 data_xdomain_port_table
Signal	Direction	Description
clk_in	Input
gate_in	Input
data_in[size-1:0]	Input
clk_out	Input
gate_out	Output
data_out[size-1:0]	Output

Implementation and use

The portable Verilog implementation can be found in data_xdomain Source File

Timing Diagram

A GTKWave-generated timing diagram is shown below:

Timing diagram