Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

circle_buf_serial

Description

Pinout

Parameters

Table 25 circle_buf_serial_param_table

Name	Min	Max	Default	Description
n_chan	?	?	12
lsb_mask	?	?	0	lsb_mask=0: chan_mask is LEFT-to-RIGHT; MSB=CH0
buf_dw	?	?	16
buf_aw	?	?	13
buf_stat_w	?	?	16
buf_auto_flip	?	?	1	auto_flip=1: Double buffers will be flipped when

Ports

Table 26 circle_buf_serial_port_table

Signal	Direction	Description
iclk	Input
reset	Input
sr_in[buf_dw-1:0]	Input	Conveyor belt carrying n_chan channels
sr_stb	Input
chan_mask[n_chan-1:0]	Input	Bitmask of channels to record. See lsb_mask parameter
wave_gate	Output
wave_dval	Output
wave_data[buf_dw-1:0]	Output
buf_sync	Output	single-cycle when buffer starts/ends
buf_transferred	Output	single-cycle when a buffer has been
buf_stop	Input	single-cycle - interrupts cbuf writing
buf_count[buf_stat_w-1:0]	Output
buf_stat2[buf_aw-1:0]	Output	includes fault bit
buf_stat[buf_stat_w-1:0]	Output	includes fault bit, and (if set) the last valid location
debug_stat[buf_aw+4:0]	Output	{stb_in, boundary, btest, wbank, rbank, wr_addr}
oclk	Input
stb_out	Input
enable	Output
read_addr[buf_aw-1:0]	Input	nominally 8192 locations
d_out[buf_dw-1:0]	Output

Implementation and use

The portable Verilog implementation can be found in circle_buf_serial Source File

Timing Diagram

A GTKWave-generated timing diagram is shown below: