Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
iirFilter
Description
Infinite Impulse Response Filter
Chain of biquad elements
Pinout
Parameters
Name |
Min |
Max |
Default |
Description |
|---|---|---|---|---|
STAGES |
? |
? |
||
DATA_WIDTH |
? |
? |
||
DATA_COUNT |
? |
? |
||
COEFFICIENT_WIDTH |
? |
? |
||
DEBUG |
? |
? |
||
STAGE_ADDRESS_WIDTH |
? |
? |
Ports
Signal |
Direction |
Description |
|---|---|---|
sysClk |
Input |
|
sysGPIO_Strobe |
Input |
|
sysGPIO_Out[31:0] |
Input |
|
dataClk |
Input |
|
S_TDATA[(DATA_COUNT*DATA_WIDTH)-1:0] |
Input |
|
S_TVALID |
Input |
|
S_TREADY |
Output |
|
M_TDATA[(DATA_COUNT*DATA_WIDTH)-1:0] |
Output |
|
M_TVALID |
Output |
|
M_TREADY |
Input |
Implementation and use
The portable Verilog implementation can be found in iirFilter Source File
Timing Diagram
A GTKWave-generated timing diagram is shown below:
