Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

host_averager

Pinout

Schematic symbol

Ports

Table 69 host_averager_port_table
Signal	Direction	Description
clk	Input
data_in[23:0]	Input
data_s	Input
read_s	Input
data_out[31:0]	Output

Implementation and use

The portable Verilog implementation can be found in host_averager Source File

Timing Diagram

A GTKWave-generated timing diagram is shown below:

Timing diagram