Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
iq_chain4
Description
Filters and decimates four I-Q multiplexed data streams
down to a single data path
Uses second-order CIC filtering.
Larry Doolittle, LBNL, 2014
Pinout
Ports
Signal |
Direction |
Description |
|---|---|---|
clk |
Input |
|
sync |
Input |
|
in1[17:0] |
Input |
|
in2[17:0] |
Input |
|
in3[17:0] |
Input |
|
in4[17:0] |
Input |
|
out[21:0] |
Output |
Implementation and use
The portable Verilog implementation can be found in iq_chain4 Source File
Timing Diagram
A GTKWave-generated timing diagram is shown below:
