Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
cic_simple_us
Description
Simple first-order CIC filter and decimator
Note that this module is configured with unsigned input and output!
Pinout
Parameters
Name |
Min |
Max |
Default |
Description |
|---|---|---|---|---|
ext_roll |
? |
? |
0 |
if set, use roll port instead of internal divider |
dw |
? |
? |
16 |
|
ex |
? |
? |
10 |
decimate by 2^ex, up to 2^ex when using ext_roll |
Ports
Signal |
Direction |
Description |
|---|---|---|
clk |
Input |
|
data_in[dw-1:0] |
Input |
|
data_in_gate |
Input |
|
roll |
Input |
sometimes unused, see ext_roll parameter |
data_out[dw-1:0] |
Output |
|
data_out_gate |
Output |
Implementation and use
The portable Verilog implementation can be found in cic_simple_us Source File
Timing Diagram
A GTKWave-generated timing diagram is shown below:
