Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

fifo

Description

blockram based FIFO

exchangeable with shortfifo.v

Pinout

Parameters

Table 56 fifo_param_table

Name	Min	Max	Default	Description
aw	?	?	3
dw	?	?	8

Ports

Table 57 fifo_port_table

Signal	Direction	Description
clk	Input
din[dw - 1: 0]	Input
we	Input
dout[dw - 1: 0]	Output
re	Input
full	Output
empty	Output
last	Output
count[aw:0]	Output

Implementation and use

The portable Verilog implementation can be found in fifo Source File