Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
saturateMath
Description
Useful modules for performing saturating arithmetic //
Expand a net’s width
Pinout
Parameters
Name |
Min |
Max |
Default |
Description |
|---|---|---|---|---|
IWIDTH |
? |
? |
8 |
|
OWIDTH |
? |
? |
12 |
Ports
Signal |
Direction |
Description |
|---|---|---|
I[IWIDTH-1:0] |
Input |
|
O[OWIDTH-1:0] |
Output |
Implementation and use
The portable Verilog implementation can be found in saturateMath Source File