Attention
This documentation is a work in progress. Expect to see errors and unfinished things.
shortfifo
Description
Short (2-32 long) FIFO meant to be efficiently implemented with
Xilinx SRL16E or similar
Except for the unified clock and the count output port,
this is pin-compatible with ordinary fifo.v
max. elements: 2**aw
Pinout
Parameters
Name |
Min |
Max |
Default |
Description |
|---|---|---|---|---|
dw |
? |
? |
8 |
|
aw |
? |
? |
3 |
Ports
Signal |
Direction |
Description |
|---|---|---|
clk |
Input |
|
din[dw-1:0] |
Input |
|
we |
Input |
|
dout[dw-1:0] |
Output |
|
re |
Input |
|
full |
Output |
|
empty |
Output |
|
last |
Output |
|
count[aw:0] |
Output |
-1: empty, 0: single element, 2**aw - 1: full |
Implementation and use
The portable Verilog implementation can be found in shortfifo Source File