Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

fiq_interp

Description

Name: IQ interpolator

% Takes interleaved I-Q, produces interpolated,

% separate streams ready for upconversion

Pinout

Parameters

Table 58 fiq_interp_param_table

Name	Min	Max	Default	Description
a_dw	?	?	16
i_dw	?	?	17
q_dw	?	?	17

Ports

Table 59 fiq_interp_port_table

Signal	Direction	Description
clk	Input
a_data[a_dw-1:0]	Input	Interleaved I-Q Data
a_gate	Input	Data valid gate
a_trig	Input	1 bit information telling data is I or Q
i_data[i_dw-1:0]	Output
i_gate	Output
i_trig	Output
q_data[q_dw-1:0]	Output
q_gate	Output
q_trig	Output
time_err	Output

Implementation and use

The portable Verilog implementation can be found in fiq_interp Source File