Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

complex_freq_wrap

Description

Pinout

Parameters

Table 29 complex_freq_wrap_param_table

Name	Min	Max	Default	Description
n_chan	?	?	12
sr_wi	?	?	40	Conveyor belt data width
shift_base	?	?	4
refcnt_w	?	?	17

Ports

Table 30 complex_freq_wrap_port_table

Signal	Direction	Description
clk	Input	single clock domain
channel_sel[1:0]	Input	0 - Field, 1 - Forward, 2 - Reverse, 3 - IQ_Fiber (from PRC)
sample_wave	Input
wave_shift[3:0]	Input
sr_valid	Input
sr_data[sr_wi-1:0]	Input
reg_freq[refcnt_w-1:0]	Output
_freq_valid	Output
reg_amp_max[16:0]	Output
reg_amp_min[16:0]	Output
_updated	Output
avg_power[23:0]	Output
avg_power_strobe	Output
_timing_err	Output

Implementation and use

The portable Verilog implementation can be found in complex_freq_wrap Source File