Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

iq_modulator

Description

Pinout

Schematic symbol

Parameters

Table 85 iq_modulator_param_table
Name	Min	Max	Default	Description
WIDTH	?	?	16
zero_bias	?	?	0

Ports

Table 86 iq_modulator_port_table
Signal	Direction	Description
clk	Input
sin[WIDTH-1:0]	Input
cos[WIDTH-1:0]	Input
d_out[WIDTH-1:0]	Output
ampi[WIDTH-1:0]	Input
ampq[WIDTH-1:0]	Input

Implementation and use

The portable Verilog implementation can be found in iq_modulator Source File