Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

sat_add

Description

Pinout

Parameters

Table 125 sat_add_param_table

Name	Min	Max	Default	Description
isize	?	?	16
osize	?	?	15

Ports

Table 126 sat_add_port_table

Signal	Direction	Description
clk	Input
a[isize-1:0]	Input
b[isize-1:0]	Input
sum[osize-1:0]	Output

Implementation and use

The portable Verilog implementation can be found in sat_add Source File