Attention

This documentation is a work in progress. Expect to see errors and unfinished things.

doublediff1

Description

Pinout

Parameters

Table 47 doublediff1_param_table

Name	Min	Max	Default	Description
dw	?	?	28
gw	?	?	1
dsr_len	?	?	4

Ports

Table 48 doublediff1_port_table

Signal	Direction	Description
clk	Input
reset	Input
d_in[dw-1:0]	Input
g_in[gw-1:0]	Input
d_out[dw-1:0]	Output
g_out[gw-1:0]	Output

Implementation and use

The portable Verilog implementation can be found in doublediff1 Source File